1. Field of the Invention
The invention generally relates to a memory structure, and in particular, the present invention relates more to a memory array including buried word lines for dynamic random access memory devices.
2. Description of the Prior Art
A Dynamic Random Access Memory (DRAM) is an essential element in many electronic products. In a DRAM, numerous memory cells comprise array regions which can be used to store data. Each memory cell consists of a metal oxide semiconductor (MOS) electrically connected in series to a capacitor wherein the capacitor has a storage node which is electrically connected to a conductive material of a node contact, thereby forming a storage channel when coupled with a MOS drain; this way, data can be relayed between the capacitor and the digit line in the control of a word line.
With the trends of shrinking dimensions of the memory cells, a variety of DRAM layouts is provided. In one type of the DRAM layouts, active regions include all two memory cells, which are arranged alternatively. Two word lines pass through a same active region and areas overlapped between the word lines and the active regions are used as gate structures. A digit line contact plug is disposed between the two memory cells and is electrically connected to the active region and a digit line. As we know, in this case, one digit line engages two memory cells. Although various designs of memory arrays are provided, there is always a continuing need for developing a novel memory layout structure and memory structures that have a relatively high integration ratio of memory cells.